Automated Design Techniques for Low-Power High-Speed Circuits On a Self-Configuring 64-bit Wallace Tree Multiplier

This paper presents techniques to reduce power consumption in arithmetic logic units (ALUs) while improving performance. This ultimate paradigm in design takes advantage of varying input widths to enable evaluation with partial ALU activation. We will demonstrate partial ALU evaluations have shorter critical paths; this thus enables us to increase clock speed. Shorter clock time means the circuit can spend less time in operation mode and more time in power savings mode such as sleep mode or clock gating mode. These proposed techniques will be implemented and benchmarked on various large-input dynamic Wallace Tree multipliers using 90nm technology. Additional power saving circuitry, influenced by static CMOS sleep mode circuits and clock gating in dynamic logic, are added onto an existing dynamic Wallace Tree multiplier. These proposed additions look at the incoming input bits and determines which part of the tree to “precharge” using a self-generated variable clock. This design encompasses the philosophy of “off until used” by using the partial tree for partial computations. The goal is to see if these proposed circuit additions significantly reduce leakage power while increasing overall performance. ____________________________________________________________________________________________________